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Software & Driver


5.3.16 - SPI

Control command sends and receives serial data using SPI synchronous communication.

Table 5.3.16-1. SPI Command Response

0 Checksum8  
1 0xF8  
2 4 + NumSPIWords  
3 0×3A  
4 Checksum16 (LSB)  
5 Checksum16 (MSB)  
6 SPIOptions  
    Bit 7: AutoCS
    Bit 6: DisableDirConfig
    Bits 1-0: SPIMode (0=A, 1=B, 2=C, 3=D)
7 SPIClockFactor  
8 Reserved  
9 CSPinNum  
10 CLKPinNum  
11 MISOPinNum  
12 MOSIPinNum  
13 NumSPIBytesToTransfer  
14 SPIByte0  
0 Checksum8  
1 0xF8  
2 1 + NumSPIWords  
3 0×3A  
4 Checksum16 (LSB)  
5 Checksum16 (MSB)  
6 Errorcode  
7 NumSPIBytesTransferred  
8 SPIByte0  
  • NumSPIWords: This is the number of SPI bytes divided by 2. If the number of SPI bytes is odd, round up and add an extra zero to the packet.
  • SPIOptions: If AutoCS is true, the CS line is automatically driven low during the SPI communication and brought back high when done. If DisableDirConfig is true, this function does not set the direction of the lines, whereas if it is false the lines are configured as CS=output, CLK=output, MISO=input, and MOSI=output. SPIMode specifies the standard SPI mode as discussed below.
  • SPIClockFactor: Sets the frequency of the SPI clock according the following approximate formula: Frequency = 1000000/(8+10*(256-SPIClockFactor), where passing a value of 0 corresponds to a factor of 256, and thus a maximum frequency of about 125 kHz.
  • CS/CLK/MISO/MOSI -PinNum: Assigns which digital I/O line is used for each SPI line. Value passed is 0-22 corresponding to the normal digital I/O numbers as specified in Section 2.9.
  • NumSPIBytesToTransfer: Specifies how many SPI bytes will be transferred (1-240).

The initial state of SCK is set properly (CPOL), by this function, before CS (chip select) is brought low (final state is also set properly before CS is brought high again). If CS is being handled manually, outside of this function, care must be taken to make sure SCK is initially set to CPOL before asserting CS.

All standard SPI modes supported (A, B, C, and D).

Mode A: CPOL=0, CPHA=0
Mode B: CPOL=0, CPHA=1
Mode C: CPOL=1, CPHA=0
Mode D: CPOL=1, CPHA=1

If Clock Phase (CPHA) is 1, data is valid on the edge going to CPOL. If CPHA is 0, data is valid on the edge going away from CPOL. Clock Polarity (CPOL) determines the idle state of SCK.

Up to 240 bytes can be written/read. Communication is full duplex so 1 byte is read at the same time each byte is written.