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2.10.2 - Timer Operation/Performance Notes

Note that the specified timer clock frequency is the same for all timers. That is, TimerClockBase and TimerClockDivisor are singular values that apply to all timers. Modes 0, 1, 2, 3, 4, 7, 12, and 13, all are affected by the clock frequency, and thus the simultaneous use of these modes has limited flexibility. This is often not an issue for modes 2 and 3 since they use 32-bit registers.

The output timer modes (0, 1, and 7) are handled totally by hardware. Once started, no processing resources are used and other UE9 operations do not affect the output. The major exception to this is if the TimerCounter UpdateConfig bit is set as described earlier, as that will cause all output timers to stop and restart.

The edge-detecting timer input modes do require UE9 processing resources, as an interrupt is required to handle each edge. Timer modes 2, 3, 5, 6, 9, 12, and 13 must process every applicable edge (rising or falling). Timer modes 4 and 8 must process every edge (rising and falling). To avoid missing counts, keep the total number of processed edges (all timers) less than 100,000 per second. That means that in the case of a single timer, there should be no more than 1 edge per 10 μs. For multiple timers, all can process an edge simultaneously, but if for instance 6 timers get an edge at the same time, 60 μs should be allowed before any further edges are applied. If streaming is occurring at the same time, the maximum edge rate will be less (25,000 per second), and since each edge requires processing time the sustainable stream rates can also be reduced.