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2.10.1.6 - Firmware Counter Input With Debounce (Mode 6)

Intended for frequencies less than 10 Hz, this mode adds a debounce feature to the firmware counter, which is particularly useful for signals from mechanical switches. On every applicable edge seen by the external pin, this mode increments a 32-bit register. Unlike the pure hardware counters, these timer counters require that the firmware jump to an interrupt service routine on each edge.

When configuring only (UpdateConfig=1), the low byte of the timer value is a number from 0-255 that specifies a debounce period in 87 ms increments (plus an extra 0-87 ms of variability):

Debounce Period = (0-87 ms) + (TimerValue * 87 ms)

In the high byte (bits 8-16) of the timer value, bit 0 determines whether negative edges (bit 0 clear) or positive edges (bit 0 set) are counted.

Assume this mode is enabled with a value of 1, meaning that the debounce period is 87 ms and negative edges will be counted. When the input detects a negative edge, it increments the count by 1, and then waits 87 ms before re-arming the edge detector. Any negative edges within the 87 ms debounce period are ignored. This is good behavior for a normally-high signal where a switch closure causes a brief low signal. The debounce period can be set long enough so that bouncing on both the switch closure and switch open is ignored.

When only updating and not configuring, writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.