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2.9 - Timers/Counters

Timers / Counters Overview

The U6 has 4 timers (Timer0-Timer3) and 2 counters (Counter0-Counter1). When any of these timers or counters are enabled, they take over an FIO/EIO line in sequence (Timer0, Timer1, Timer2, Timer3, Counter0, then Counter1), starting with FIO0+TimerCounterPinOffset. The valid range for TimerCounterPinOffset is 0-8, so Timer0 can appear on FIO0-EIO0, and the highest I/O ever used would be EIO5 for Counter1 if all 4 timers and both counters are enabled. Some examples:

1 Timer enabled, Counter0 disabled, Counter1 disabled, and TimerCounterPinOffset=0:
FIO0=Timer0

1 Timer enabled, Counter0 disabled, Counter1 enabled, and TimerCounterPinOffset=0:
FIO0=Timer0
FIO1=Counter1

2 Timers enabled, Counter0 enabled, Counter1 enabled, and TimerCounterPinOffset=8:
EIO0=Timer0
EIO1=Timer1
EIO2=Counter0
EIO3=Counter1

Timers and counters can appear on various pins, but other I/O lines never move. For example, Timer1 can appear anywhere from FIO1 to EIO1, depending on TimerCounterPinOffset. On the other hand, FIO2 (for example), is always on the screw terminal labeled FIO2.

Applicable digital I/O are automatically configured as input or output as needed when timers and counters are enabled, and stay that way when the timers/counters are disabled.

Timers and counters use digital I/O hardware so the digital I/O specs from Appendix A apply.  An input recognizes 0.0-0.8V as low and 2.0-5.8V as high, so rising and falling edges must transition between those levels.  For more information about signal connections see Section 2.8.1.

There are special channels numbers that can be used to read timer and counter values.  These channel numbers can be used most places where you would use analog input channel numbers, such as LJLogUD and LJStreamUD.  See Section 3.2.1 for more information.

 

Timers

The timers (Timer0-Timer3) have various modes available.  These are listed in the following table and more details can be found in Section 2.9.1.

Table 2.9-1. U6 Timer modes

Index (Low-level & UD) 
0 16-bit PWM output
1 8-bit PWM output
2 Period input (32-bit, rising edges)
3 Period input (32-bit, falling edges)
4 Duty cycle input
5 Firmware counter input
6 Firmware counter input (with debounce)
7 Frequency output
8 Quadrature input
9 Timer stop input (odd timers only)
10 System timer low read (Default mode)
11 System timer high read
12 Period input (16-bit, rising edges)
13 Period input (16-bit, falling edges)
14 Line-to-Line input

 

All timers use the same timer clock. There are 7 choices for the timer base clock:

Table 2.9-2. U6 Timer clock base options

Index (Low-level/UD) 
0/20 4 MHz
1/21 12 MHz
2/22 48 MHz (Default)
3/23 1 MHz /Divisor
4/24 4 MHz /Divisor
5/25 12 MHz /Divisor
6/26 48 MHz /Divisor

The first 3 clocks have a fixed frequency, and are not affected by TimerClockDivisor. The frequency of the last 4 clocks can be further adjusted by TimerClockDivisor, but when using these clocks Counter0 is not available. When Counter0 is not available, it does not use an external FIO/EIO pin. The divisor has a range of 0-255, where 0 corresponds to a division of 256.

 

Counters

Each counter (Counter0 or Counter1) consists of a 32-bit register that accumulates the number of falling edges detected on the external pin. If a counter is reset and read in the same function call, the read returns the value just before the reset.

Note that Counter0 is not available with certain timer clock base frequencies. In such a case, it does not use an external FIO/EIO pin. An error will result if an attempt is made to enable Counter0 when one of these frequencies is configured. Similarly, an error will result if an attempt is made to configure one of these frequencies when Counter0 is enabled.

 

11 comments

"...AIN3 is always on the screw terminal labeled FIO3."

Is this a typo?  I don't see where AIN3 was mentioned anywhere before in the article.  

Fixed.  I think that was a copy/past mistake from the U3 User's Guide.  On the U3, AIN3/FIO3 share the same terminal.

"Both timers use the same timer clock."

Another copy/paste error I guess, assuming there are really four timers. 

Fixed it.  Thanks.

Hello, back again.  Just want to clarify something.

The way I'm reading the documentation,

"For example, Timer1 can appear anywhere from FIO1 to EIO1, depending on TimerCounterPinOffset"

by inference, counter0's max offset puts it on EI04,  counter1 on EI05.  

And nothing can be assigned on EI06 and above.   So the max TimerCounterPinOffset must be a

f(numberofactivetimers + numberofactivecounters)

Is this correct?  I ask because such a rule that seems arbitrary would merit extra description.

At least a statement to the effect 'no timers and counters may have an offset the puts their assignment on EI06 or higher' 

Thanks

 

I think the missing detail was that the valid range for TimerCounterPinOffset is 0-8.  That is the constraining rule and the reason that Timers/Counters will never be above EIO5 on the U6.  I added this to the first paragraph above.

Thanks.  Still have a question though.  If I tried to config all four timers and both counters at offset 7 ie FIO7 (non-division base), which error code would be returned because the last assignment, counter1 I assume, would have to be on EIO4?

 

There would be no error generated in this condition.

  • FIO7 - T0
  • EIO0 - T1
  • EIO1 - T2
  • EIO2 - T3
  • EIO3 - C0
  • EIO4 - C1

That is a valid setup. Even setting the offset to 8 is still a valid setup.

My response from yesterday and the text added to the section was from the standpoint of only having 2 timers, like the U3, but the U6 has 4 timers so I corrected the section text and the comment.

jthurbs's picture

What is the speed of the counters? How close can two falling edges be before the counter is unable to register both of them?

Thanks much

LabJack Support's picture

The limit for hardware counters is stated in Appendix A as an 8 Mhz 0/3.3V square wave, so the low time and high time must both be at least 125ns.  Speed is worse at less than 3.3V and better at greater than 3.3V.

For timers, including timers configured in the Firmware Counter mode, see Section 2.9.2.