2.9.1.4 - Duty Cycle Measurement (Mode 4) [U3 Datasheet] | LabJack

# 2.9.1.4 - Duty Cycle Measurement (Mode 4) [U3 Datasheet]

Records the high and low time of a signal on the external pin, which provides the duty cycle, pulse width, and period of the signal.  Returns 4 bytes, where the first two bytes (least significant word or LSW) are a 16-bit value representing the number of clock ticks during the high signal, and the second two bytes (most significant word or MSW) are a 16-bit value representing the number of clock ticks during the low signal.  The clock frequency is determined by TimerClockBase/TimerClockDivisor.

The appropriate value is updated on every edge, so a read returns the most recent high/low times.  Note that a duty cycle of 0% or 100% does not have any edges.

To select a clock frequency, consider the longest expected high or low time, and set the clock frequency such that the 16-bit registers will not overflow.  In other words, to measure 0% to 100% duty cycle for a given signal frequency, you need to set your clock frequency low enough such that the overall period of the signal is less than 65535 * 1/TimerClockFrequency.  That equates to:

fclock    65535 * fsignal

Note that the minimum measurable high/low time is limited by the edge rate limit discussed in Section 2.9.2.

When using the LabJackUD driver the value returned is the entire 32-bit value.  To determine the high and low time this value should be split into a high and low word.  One way to do this is to do a modulus divide by 2^16 to determine the LSW, and a normal divide by 2^16 (keep the quotient and discard the remainder) to determine the MSW.

Writing a value of zero to the timer performs a reset.  After reset, a read of the timer value will return zero until a new edge is detected.  If a timer is reset and read in the same function call, the read returns the value just before the reset.  The duty cycle reset is special, in that if the signal is low at the time of reset, the high-time/low-time registers are set to 0/65535, but if the signal is high at the time of reset, the high-time/low-time registers are set to 65535/0.  Thus if no edges occur before the next read, it is possible to tell if the duty cycle is 0% or 100%.

Edge Rate Limits

This edge-detecting timer mode requires processing resources as an interrupt is required to handle each edge.  See more about edge rate limits in Section 2.9.2.