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2.9 - Timers/Counters

The U3 has 2 timers (Timer0-Timer1) and 2 counters (Counter0-Counter1). When any of these timers or counters are enabled, they take over an FIO/EIO line in sequence (Timer0, Timer1, Counter0, then Counter1), starting with FIO0+TimerCounterPinOffset. Some examples:

1 Timer enabled, Counter0 disabled, Counter1 disabled, and TimerCounterPinOffset=4:

1 Timer enabled, Counter0 disabled, Counter1 enabled, and TimerCounterPinOffset=6:

2 Timers enabled, Counter0 enabled, Counter1 enabled, and TimerCounterPinOffset=8:

Starting with hardware revision 1.30, timers/counters cannot appear on FIO0-3, and thus TimerCounterPinOffset must be 4-8. A value of 0-3 will result in an error. This error can be suppressed by a power-up default setting in LJControlPanel. If suppressed, a 0-3 will result in an offset of 4.

Timers and counters can appear on various pins, but other I/O lines never move. For example, Timer1 can appear anywhere from FIO4 to EIO1, depending on TimerCounterPinOffset and whether Timer0 is enabled. On the other hand, FIO5 (for example), is always on the screw terminal labeled FIO5, and AIN5 (if enabled) is always on that same screw terminal.

Note that Counter0 is not available with certain timer clock base frequencies (those that support a divisor). In such a case, it does not use an external FIO/EIO pin. An error will result if an attempt is made to enable Counter0 when one of these frequencies is configured. Similarly, an error will result if an attempt is made to configure one of these frequencies when Counter0 is enabled.

Applicable digital I/O are automatically configured as input or output as needed when timers and counters are enabled, and stay that way when the timers/counters are disabled.

See Section 2.8.1 for information about signal connections.

Each counter (Counter0 or Counter1) consists of a 32-bit register that accumulates the number of falling edges detected on the external pin. If a counter is reset and read in the same function call, the read returns the value just before the reset.

The timers (Timer0-Timer1) have various modes available:

Table 2.9-1. U3 Timer Modes

Index (Low-level & UD)  
0 16-bit PWM output
1 8-bit PWM output
2 Period input (32-bit, rising edges)
3 Period input (32-bit, falling edges)
4 Duty cycle input
5 Firmware counter input
6 Firmware counter input (with debounce)
7 Frequency output
8 Quadrature input
9 Timer stop input (odd timers only)
10 System timer low read (default mode)
11 System timer hight read
12 Period input (16-bit, rising edges)
13 Period input (16-bit, falling edges)
14 Line-to-Line input

Both timers use the same timer clock.
There are 7 choices for the timer clock base:

Table 2.9-2. U3 Timer Clock Base Options

Index (Low-level/UD)  
0 / 20 4 MHz
1 / 21 12 MHz
2 / 22 48 MHz (default)
3 / 23 1 MHz /Divisor (Counter0 not available)
4 / 24 4 MHz /Divisor (Counter0 not available)
5 / 25 12 MHz /Divisor (Counter0 not available)
6 / 26 48 MHz /Divisor (Counter0 not available)

Note that these clocks apply to the U3 hardware revision 1.21+. With hardware revision 1.20 all clocks are half of the values above.

The first 3 clocks have a fixed frequency, and are not affected by TimerClockDivisor. The frequency of the last 4 clocks can be further adjusted by TimerClockDivisor, but when using these clocks Counter0 is not available. When Counter0 is not available, it does not use an external FIO/EIO pin. The divisor has a range of 0-255, where 0 corresponds to a division of 256.

Note that the DACs (Section 2.7) are derived from PWM signals that are affected by the timer clock frequency. The default timer clock frequency of the U3 is set to 48 MHz, as this results in the minimum DAC output noise. If the frequency is lowered, the DACs will have more noise, where the frequency of the noise is the timer clock frequency divided by 216.


The "noise" created on the DAC's outputs when generating frequencies actually seems to make the DAC's useless. I was attempting to generate a frequency between 100 and 1,000 Hz (Timer0 mode 7) and modulate it in hardware using the amplitude from DAC0, but the "noise" at this frequency has a 5 volt amplitude. Is this to be expected, or am I experiencing something unexpected?

A couple solutions are a large capacitor from DACn to GND and using 8-bit DAC mode.  See the 4th paragraph in Section 2.7.

The good news is the U6 does not have this problem and we will make sure to use it in any application that requires a DAC and square wave generation that involve lower than 48MHz frequencies. At 500 Hz a 3,300µF cap on the DAC output was far from sufficient (for more info see: http://www.unc.edu/~ogmonbur/lj/lj-docs/lj-info0.html#U3_DAC_Noise )

I am using the example timer/counter program that was given for visual basic for the U3 device.

Instead of using Timer0, I plugged an external function generator into Counter1. When it records the count it has about an error of an extra .5% during the first count but only an error of an extra .02% on the second count. Why is it that it isn't exactly counting the amount coming in? And also, why is it that the errors aren't the same for each count.

If you don't understand, please just say so and I will try to explain better.


What frequency are you providing with your function generator?  What sort of numbers do you get for the 1st read and 2nd read?

For Frequency of 1 MHz get avg of 10049113 for first and 20050821 for second (difference of 10001708, which is not the same error as the first read). 

For Frequency of 0.5 MHz get avg of 5026047 for first and 10026894 for second (difference of 5000847, which again is not the same error as the first read).

The Max frequency it says it can handle according to the specs is 8 MHz

Also I am having trouble coding the counters myself, but this is using your built in example so I thought it would work.

Thanks for responding so quickly.

For the 1st read, you are getting counts from when the counter was enabled to the read.  That means the 1000 second sleep plus other code.  For the first read this includes the configuration code, so that likely explains why the first read is higher than the second.  If you are trying to measure frequency, see the Frequency Measurement forum post for general ideas and tips.

julester23's picture

Chapter discusses mode 14 (line-to-line) but this is missing in your table of of modes in chapter 2.9.

LabJack Support's picture

Added now.  Thanks.