2.8 - Digital I/O [U3 Datasheet] | LabJack
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2.8 - Digital I/O [U3 Datasheet]

Digital I/O Overview

The LabJack U3 has up to 20 digital I/O channels. 16 are available from the flexible I/O lines, and 4 dedicated digital I/O (CIO0-CIO3) are available on the DB15 connector. The first 4 lines, FIO0-FIO3, are unavailable on the U3-HV. Each digital line can be individually configured as input, output-high, or output-low. The digital I/O use 3.3 volt logic and are 5 volt tolerant. See our Configuration and Digital I/O pseudocode pages for programming guidance.

The LabJackUD driver uses the following bit numbers to specify all the digital lines:

0-7    FIO0-FIO7  (0-3 unavailable on U3-HV)
8-15   EIO0-EIO7
16-19  CIO0-CIO3

The "F", "E", and "C" designators have little special meaning.  They are just arbitrary letters used to designate different groupings of digital I/O.  The generic designator DIOx is sometimes used to describe any digital I/O from 0 to 19, so for example an alternative name for EIO0 is DIO8.

The 8 FIO lines appear on the built-in screw-terminals, while the 8 EIO and 4 CIO lines appear only on the DB15 connector. See the DB15 Section of this User’s Guide for more information.


Max Current & Overvoltage Protection

All the digital I/O include an internal series resistor that provides overvoltage/short-circuit protection. These series resistors also limit the ability of these lines to sink or source current. Refer to the specifications in Appendix A.


Tri-State I/O

All digital I/O on the U3 have 3 possible states: input, output-high, or output-low. Each bit of I/O can be configured individually. When configured as an input, a bit has a ~100 kΩ pull-up resistor to 3.3 volts (all digital I/O are 5 volt tolerant). When configured as output-high, a bit is connected to the internal 3.3 volt supply (through a series resistor). When configured as output-low, a bit is connected to GND (through a series resistor).

When only lightly loaded, an input terminal will measure about 3.3 volts if measured with a DMM, and thus it can be tough to use a DMM to tell whether a line is set to input or output-high.  A couple tips to tell the difference:

1. Look for a slight change where output-high measures a little higher. For example, a DMM might show 3.300 for input and 3.315 for output-high.

2. Add a load resistor. If you add a 100k from DIOx to GND, it should read about 1.6V for input and 3.3V for output-high.


5 Volt Output

The fact that the digital I/O are specified as 5-volt tolerant means that 5 volts can be connected to a digital input without problems (see the actual limits in the specifications in Appendix A). If 5 volts is needed from a digital output, consider the following solutions:

  • Use the LJTick-DigitalOut5V to convert a pair of digital outputs to 5V logic.
  • In some cases, an open-collector style output can be used to get a 5V signal.  To get a low set the line to output-low, and to get a high set the line to input (... note that this does not work with timer outputs, e.g. PWM, as they toggle the line between output-low and output-high).  When the line is set to input, the voltage on the line is determined by a pull-up resistor.  The U3 has an internal ~100k resistor to 3.3V, but an external resistor can be added to a different voltage.  Whether this will work depends on how much current the load is going to draw and what the required logic thresholds are. Say for example a 10k resistor is added from EIO0 to VS. EIO0 has an internal 100k pull-up to 3.3 volts and a series output resistance of about 180 ohms. Assume the load draws just a few microamps or less and thus is negligible. When EIO0 is set to input, there will be 100k to 3.3 volts in parallel with 10k to 5 volts, and thus the line will sit at about 4.85 volts. When the line is set to output-low, there will be 180 ohms in series with the 10k, so the line will be pulled down to about 0.1 volts.
  • A surefire way to get 5 volts from a digital output is to add a simple logic buffer IC that is powered by 5 volts and recognizes 3.3 volts as a high input. Consider the CD74ACT541E from TI (or the inverting CD74ACT540E). All that is needed is a few wires to bring VS, GND, and the signal from the LabJack to the chip. This chip can level shift up to eight 0/3.3 volt signals to 0/5 volt signals and provides high output drive current (+/-24 mA).
  • Note that the 2 DAC channels on the U3 can be set to 5 volts, providing 2 output lines with such capability.


Basic Tests

For basic testing use the Test Panel in LJControlPanel to change the state of a particular DIO while using a DMM to measure the voltage of that DIO versus GND. (Make sure DMM leads are properly connected.)

Below are typical voltages with:

  • No load
  • 1k resistor from DIO to GND
  • 1k resistor from DIO to VS

The values are a little different for FIO versus EIO/CIO as the latter has less series impedance.

  FIO vs GND with no load
  Input 3.28 volts
  Output-low 0.02 volts
  Output-high 3.30 volts
  FIO vs GND with a 1k resistor installed FIO to GND
  Input 0.025 volts
  Output-low 0.015 volts
  Output-high 2.2 volts
  FIO vs GND with a 1k resistor installed FIO to VS
  Input 5.0 volts
  Output-low 1.7 volts
  Output-high 3.9 volts
  EIO/CIO vs GND with no load
  Input 3.29 volts
  Output-low 0.03 volts
  Output-high 3.30 volts
  EIO/CIO vs GND with a 1k resistor installed EIO/CIO to GND
  Input 0.025 volts
  Output-low 0.027 volts
  Output-high 2.9 volts
  EIO/CIO vs GND with a 1k resistor installed EIO/CIO to VS
  Input 5.0 volts
  Output-low 0.6 volts
  Output-high 3.6 volts


Boot-Up Defaults

The power-up condition of the digital I/O can be configured by the user with the "Config Defaults" option in LJControlPanel.  From the factory, all digital I/O are configured to power-up as inputs. Note that even if the power-up default for a line is changed to output-high or output-low, there is a delay of about 5 ms at power-up where all digital I/O are in the factory default condition.  For more information see this forum topic.


Why Are My Digital I/O "High" at Boot-Up?

The implied question here is "why do my DIO boot up as output-high from the factory".  The answer is that per the "Boot-Up Defaults" section above the factory default state for all DIO is input, but since inputs have a 100k internal pull-up they will read 3.3 volts if only lightly loaded.  So likely you are seeing that the state of your DIO is input, not output-high.  Also see the "Tri-State I/O" section above.


Making An Input Read Low By Default

If you want a floating digital input to read low, an external pull-down resistor can be added to overpower the internal 100k pull-up.  4.7k to 22k would be a typical range for this pull-down, with 10k being a solid choice for most applications.


Software Interface

The low-level Feedback function (Section 5.2.5) writes and reads all digital I/O. For information about using digital I/O under the Windows LabJackUD driver, see Section 4.3.5. See Section 3 for timing information.


Bit-Packed Integers

Many function parameters contain specific bits within a single integer parameter to write/read specific information. In particular, most digital I/O parameters contain the information for each bit of I/O in one integer, where each bit of I/O corresponds to the same bit in the parameter (e.g. the direction of FIO0 is set in bit 0 of parameter FIODir). For instance, in the low-level function ConfigU3, the parameter FIODirection is a single byte (8 bits) that writes/reads the power-up direction of each of the 8 FIO lines:

  • if FIODirection is 0, all FIO lines are input,
  • if FIODirection is 1 (20), FIO0 is output, FIO1-FIO7 are input,
  • if FIODirection is 5 (20 + 22), FIO0 and FIO2 are output, all other FIO lines are input,
  • if FIODirection is 255 (20 + … + 27), FIO0-FIO7 are output.





If I connect an EIO digital line to the VSS (that is 5V) and then inadvertently set to output-low.

This is an equivalent of a ground connection through a 180 Ω resistance.

This will draw 5 V / 180 Ω= 0.028 A = 28 mA from the board. Is this lethal?


In other words, how much intensity can we safely draw from the digital outputs?

More generally is there some settings or hardware mistakes that will break the device and that we should be aware off?


The U3 should not be able to damage itself.  You should be able to connect any I/O to anything else without causing damage.  Your example is perhaps the worst thing the U3 can do to itself, but the I/O line should be able to sink the 28 mA continuously without damage.

The most common mistakes that cause damage are when you connect things that have other power supplies, particularly higher voltage supplies or AC mains.

Forgive me if I've overlooked a spec somewhere, but I can't seem to find the speed of this DIO. For example, if I were to start with a DIO set to output low, and send back-to-back commands of output high, then output low, about what would be the width of the pulse, without a load? with a 1kΩ load?

Thank you in advance!

There are 3 ways to make a pulse like that:

    - Command/Response:  Software command to set it high followed by command to set it low.  Per Section 3.1 the best you can do is about 600us per command.

    - WAIT:  Software sends a single command that does high-wait-low.  See the description of iotype LJ_ioPUT_WAIT in Section 4.3.14 and search labjack.com using the term "LJ_ioPUT_WAIT" for some forum topics.  This provides a resolution of 128us, so that would be the minimum controlled pulse width.  If you just did a high-low with no wait, the pulse width would probably be on the order of 1us and might be so fast you don't even see it rise fully.

    - Timer:  Use a PWM output or frequency output timer to create one or more pulses.  If you want exact control over how many pulses, use another timer in stop mode.  Start in Section 2.9.   You can get crazy narrow pulses using this technique, to the extent that you will see the limitations of the time constant created by inherent capacitance and any added load capacitance.

Note that with the first 2 techniques you could use port iotypes rather than bit iotypes, and thus update multiple DIO at the same time.

I would not expect load resistance to have much effect on speed.  It will cause the voltage to be reduced less than 3.3V due to a voltage-divider effect with the internal output impedance.  See note #13 in Appendix A.