2.7 - DAC [U3 Datasheet] | LabJack
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2.7 - DAC [U3 Datasheet]

DAC Overview

The LabJack U3 has 2 analog outputs (DAC0 and DAC1) that are available on the screw terminals.  Each analog output can be set to a voltage between about 0.04 and 4.95 volts with 10 bits of resolution (8 bits on older hardware revision 1.20/1.21).  The maximum output voltage is limited by the supply voltage to the U3.

See our Configuration and Analog Outputs pseudocode pages for programming guidance.

Starting with hardware revision 1.30 (2008), DAC1 is always enabled and does not affect the analog inputs, but with older hardware the second analog output is only available in certain configurations. With hardware revisions <1.30, if the analog inputs are using the internal 2.4 volt reference (the most accurate option), then DAC1 outputs a fixed voltage of 1.5*Vref.  Also with hardware revisions <1.30, if DAC1 is enabled the analog inputs use Vreg (3.3 volts) as the ADC reference, which is not as stable as the internal 2.4 volt reference. 

The DAC outputs are derived as a percentage of Vreg, and then amplified by 1.5, so any changes in Vreg will have a proportionate affect on the DAC outputs.  Vreg is more stable than Vs (5 volt supply voltage), as it is the output from a 3.3 volt regulator.

The DACs are derived from PWM signals converted to DC with a 2nd order low pass filter.  With the default timer clock of 48 MHz, the PWM frequency is 732 Hz and the output filter with a 16 Hz cutoff frequency works great.  If the timer clock is lowered, which might be done for desired behavior on Timer0 & Timer1  (Section 2.9), the DACs will have more noise where the frequency of the noise is the timer clock frequency divided by 65536.  This effect is more exaggerated with the 10-bit DACs on hardware revision 1.30+, compared to the 8-bit DACs on previous hardware revisions.  The noise with a timer clock of 48/12/4/1 MHz is roughly 5/20/100/600 mV.  If lower noise performance is needed at lower timer clock frequencies, use the power-up default setting in LJControlPanel to force the device to use 8-bit DAC mode (uses the low-level CompatibilityOptions byte documented in Section 5.2.2), since the PWM frequency is clock/256 rather than clock/65536.  A large capacitor (at least 220 µF) from DACn to GND can also be used to reduce noise.

Each channel of PWM hardware used to create the DACs has 2 bytes available to hold the duty cycle value.  With 8-bit DACs the hardware will store the current value and new value, and switch over to the new value right at the start of a new cycle, thus assuring glitch-free operation.  With 10-bit DACs this is not possible, and the new value is applied immediately.  That means that on a DAC update to a new value a rising edge could skipped, which would result in 1 cycle of all low, which after the filter would result in a glitch that looks like a negative going spike of perhaps 100-200 mV.  If this is not acceptable use 8-bit DAC mode as mentioned in the previous paragraph.

The analog outputs have 2nd order low pass output filters with a 3 dB cutoff around 16 Hz, limiting the frequency of output waveforms to less than that, and corresponding to a step response time constant of about 10 ms.  The reason for 16 Hz is that the cutoff frequency needs to be at least this low to filter the 732 Hz (default) PWM source to an acceptable DC output.

The analog output commands are sent as raw binary values (low level functions).  For a desired output voltage, the binary value can be approximated as:

Bits(uncalibrated) = (Volts/4.95)*256

For a proper calculation, though, use the calibration values (Slope and Offset) stored in the internal flash on the processor (Section 5.4):

Bits = (Slope * Volts) + Offset

The previous apply when using the original 8-bit DAC commands supported on all hardware versions.  To take advantage of the 10-bit resolution on hardware revision 1.30, new commands have been added (Section 5.2.5) where the binary values are aligned to 16-bits.  The calibration constants are still aligned to 8-bits, however, so the slope and offset should each be multiplied by 256 before using in the above formula.

The analog outputs can withstand a continuous short-circuit to ground, even when set at maximum output.  

Voltage should never be applied to the analog outputs, as they are voltage sources themselves.  In the event that a voltage is accidentally applied to either analog output, they do have protection against transient events such as ESD (electrostatic discharge) and continuous overvoltage (or undervoltage) of a few volts.

There is an accessory available from LabJack called the LJTick-DAC that provides a pair of 14-bit analog outputs with a range of ±10 volts.  The LJTick-DAC plugs into any digital I/O block, and thus up to 10 of these can be used per U3 to add 20 analog outputs.  The LJTick-DAC has various improvements compared to the built-in DACs on the U3:

  • Range of +10.0 to -10.0 volts.
  • Resolution of 14-bits.
  • Slew rate of 0.1 V/μs.
  • Based on a reference, rather than regulator, so more accurate and stable.
  • Does not affect analog inputs in any configuration.



It would be nice if Vef was available externally to drive ratiometric devices such as thermistors and potentiometers, then with the resistor networks driven by the same voltage as the ADC's the variability of the reference can be more or less excluded from the measurement.



Yes, that can be handy for some measurements where you are looking for a percentage of full scale, such as your examples of a voltage divider and potentiometer.  The problem in application, though, is that we usually can't bring out the exact same reference signal to the user.  That reference is critical to the ADC and often quite sensitive, so we would probably have to protect it and buffer it.  Now that it is buffered/protected it is not necessarily the exact same voltage seen by the ADC (could be errors introduced), so you might as well just set the DAC to the value of interest.  If the DAC accuracy is sufficient, great, if not you would measure the actual DAC voltage.

One other point is that this would only make sense on the low-voltage analog input channels on the U3-LV.  These are the only channels where the input span is 0-Vref.  On other analog inputs there is signal-conditioning.

Can the outputs (DAC) produce waveforms at 1 khz lets say.......if yes.......whats the 3d filter 16hz  for?


Thank you


There is a 16 Hz filter, so you can't produce a 1 kHz waveform.  The filter is needed to convert the PWM signals to DC voltages.

See the Waveform Generation App Note.

SO Question, probably i overlooked the manual, purchased a labjack U3-LV, using DAQfactory Express...........which channel numbers are for the dedicated analog outputs, DAQfactory express doesnt all me to configure U3, only U9, or should it be done from the LJ Control Panel?



DAC0 is channel 0 and DAC1 is channel 1.  See Section 3.4 of the DF-LJ App Guide.


is it possible to generate a PWM signal between 125 and 160Hz?

How high is the max. voltage of that signal.

We need to test specifications of electronic units. That´s why we need to measure analog inputs at the same time.

Thank you for the help.


See the Waveform Generation App Note, but generally you use timers to create PWM outputs, so see Section and Section  The timer uses a digital output so the PWM will be 0 volts low and 3.3 volts high.  If that does not work, let us know more about your load.


Is it possible to control two floating power supplies using the two analog outs of the u3 HV (harware version 1.3)

The DACs provide ~0-5 volt variable signals and are both referenced to GND.  If that works with your supplies then you are good to go.

In the text it states "For a proper calculation, though, use the calibration values (Slope and Offset) stored in the internal flash on the processor (Table 2-7):" However, I cannot find any Table 2-7 anywhere in the text on the web site.  A search of the PDF manual also shows that the only mention of the text "Table 2-7" is on page 10 in that sentence and that there is no actual table 2-7.

I corrected it to direct you to Section 5.4.  Note that the UD driver handles all that for you, so this would typically just be for lower-level communication.

I was wondering how much current the VS and DACs can supply.

See Appendix A.  In particular notes 3, 10, and 11.  The major consideration for DAC current is voltage drop across the 50 ohms of source impedance.