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Datasheets and User Guides

App Notes

Software & Driver


13.1.8 High-Speed Counter


Capable DIO: DIO16, DIO17, DIO18, DIO19 (aka CIO0, CIO1, CIO2, CIO3)

Requires Clock Source: No

Index: 7

Streamable: Yes—integer READ registers only.

T-series devices support up to 4 high-speed rising-edge counters that use hardware to achieve high count rates. These counters are shared with other resources as follows:

  • CounterA (DIO16/CIO0): Used by EF Clock0 & Clock1.
  • CounterB (DIO17/CIO1): Used by EF Clock0 & Clock2.
  • CounterC (DIO18/CIO2): Always available.
  • CounterD (DIO19/CIO3): Used by stream mode.


DIO#_EF_ENABLE: 0 = Disable, 1 = Enable
DIO#_EF_OPTIONS: Not used.
DIO#_EF_CONFIG_A: Not used.
DIO#_EF_CONFIG_B: Not used.
DIO#_EF_CONFIG_B: Not used.
DIO#_EF_CONFIG_B: Not used.


No update operations can be performed with High-Speed Counter.


Results are read from the following register.

DIO#_EF_READ_A: Returns the current count which is incremented on each rising edge.

Stream Read

All operations discussed in this section are supported in command-response mode.  In stream mode, you can read from the integer READ registers (A, B, A_AND_RESET), but as mentioned in the Stream Section those reads only return the lower 16 bits so you need to also use STREAM_DATA_CAPTURE_16 in the scan list to get the upper 16 bits.


DIO#_EF_READ_A_AND_RESET: Reads the current count then clears the counter. There is a brief period of time between reading and clearing during which edges can be missed. During normal operation this time period is 10-30 µs. If missed edges at this point are not acceptable, then do not use reset but rather just note the "virtual reset" counter value in software and subtract it from other values.

Frequency Measurement

Counters are often used to measure frequency by taking change in count over change in time:

Frequency = (CurrentCount - PreviousCount) / (CurrentTimestamp - PreviousTimestamp)

Typically the timestamps are from the host clock (software), but for more accurate timestamps read the CORE_TIMER register (address=61520, UINT32) in the same Modbus packet as the READ registers.  CORE_TIMER is a 32-bit system timer running at 1/2 the core speed, and thus is normally 80M/2 => 40 MHz.

Also note that other digital extended features are available to measure frequency by timing individual pulses rather than counting over time.


Enable CounterC on DIO18/CIO2:


Results can be read from the READ registers defined above.

Edge Rate Limits

See Appendix A-2.


Hello guys,

I need to configure the DIOs 16, 17, 18 and 19 to Highspeed Counters!
I am trying it this way:

but what about the Clock? Can I use the same clock for all DIOs? Can you explain that please?
Is it possible to configure these 4 DIOs to Highspeed Counters at the same time?

With friendly regards


High-Speed counters do not need a clock source, so all four can be enabled at the same time.


Note that EF_INDEX (formerly EF_TYPE) should be set before enabling.

Please clarify the following: High speed counter counts the rising (or falling?) edge of a signal input into DIO18 or CIO2?

Rising.  Sorry but we missed notification of this comment.  The high-speed hardware counters increment on rising edges.

See towards the top of this page, if you have Clock0 (or Clock1 & Clock2) enabled, and also have a stream running, then only CounterC is available.  If you just have a stream running, but none of the DIO-EF Clocks enabled, then 3 high-speed counters are available:  CounterA, CounterB, and CounterC.  You cannot use CounterD and stream mode at the same time, but you can stream the interrupt counters.

Thank you ,  that is clear and it is a great help.

I am streaming 3 counters now and they are all working.