Skip to main content
Skip table of contents

4.0 Hardware Overview [T-Series Datasheet]

T4 Hardware Overview

The T4 has 3 different I/O areas:

  • Communication Edge: The communication edge (top edge in Figure 4.1-1) has a USB Type-B connector and an RJ45 Ethernet connector.  Power is always provided through the USB connector, even if USB communication is not used.

  • Screw Terminal Edges: The screw terminal edges have convenient connections for the 2 analog outputs, 4 high-voltage analog inputs, and 4 flexible I/O (digital I/O, low-voltage analog inputs, or DIO-EF.  The screw terminals are arranged in blocks of 4, with each block consisting of VS, GND, and two I/O.  Also on the left screw-terminal edge are two LEDs. The Comm LED generally blinks with communication traffic, while the Status LED is used for other indications.

  • DB Edge: The DB Edge has a 15-pin female D-sub type connector (DB15) which has 12 digital I/O called EIO and CIO. The first 4 EIO lines can be configured as low-voltage analog inputs.  The first 2 EIO lines and the 4 CIO lines support some DIO-EF features (timers, counters, etc.).

Figure 4.1-1. LabJack T4

USB:  Can be used for host communication.  Power is always provided through this connector.

Ethernet:  10/100Base-T Ethernet connection can be used for host communication.

LEDs:  The Power and Status LEDs convey different information about the device.

VS:  All VS terminals are the same.  These are outputs that can be used to source about 5 volts.

GND/SGND:  All GND terminals are the same.  SGND has a self-resetting thermal fuse in series with GND.

FIO#/EIO#/CIO#:  These are the 16 digital I/O, and are also referred to as DIO4-DIO19.  Besides basic digital I/O operations, some of these terminals can be configured with Extended Features (frequency input, PWM output, etc.), some can be configured as low-voltage analog inputs, and all can be configured for various serial protocols: I2C serial, SPI serial, SBUS serial (EI-1050, SHT sensors), 1-Wire serial, and Asynchronous serial.

AIN#:  AIN0-AIN3 are the 4 high-voltage (±10V) analog inputs.

DAC#:  DAC0 & DAC1 are the 2 analog outputs.  Each DAC can be set to a voltage between about 0.01 and 5 volts with 10-bits of resolution.

For information about reading inputs, start with the Communication section.  For information about setting outputs, start with the Waveform Generation Application Note.

Figure 4.1-2. Block Diagram

T7 Hardware Overview

The T7 has 3 different I/O areas:

  • Communication Edge: The T7 has a USB Type-B connector and an RJ45 Ethernet connector.  The T7-Pro has those and also has an SMA-RP female connector and a WiFi antenna. Power is always provided through the USB connector, even if USB communication is not used.

  • Screw Terminal Edge: The screw terminal edge has convenient connections for 4 analog inputs, both analog outputs, 4 digital I/O, and both current sources. The screw terminals are arranged in blocks of 4, with each block consisting of VS, GND, and two I/O. Also on this edge are two LEDs. The Comm LED generally blinks with communication traffic, while the Status LED is used for other indications.

  • DB Edge: The DB Edge has two female D-sub type connectors: a DB15 and DB37. The DB15 has 12 digital I/O.  The DB37 has the same I/O as the screw-terminals, plus additional analog inputs and digital I/O, for a total of 14 analog inputs, 2 analog outputs, 2 fixed current sources, and 11 digital I/O.

Figure 4.2-1. Enclosure & Connectors

USB:  Can be used for host communication.  Power is always provided through this connector.

Ethernet:  10/100Base-T Ethernet connection can be used for host communication.

WiFi (T7-Pro only): 2.4 GHz 802.11 b/g WiFi connection can be use for host communication.

LEDs:  The Power and Status LEDs convey different information about the device.

VS:  All VS terminals are the same.  These are outputs that can be used to source about 5 volts.

GND/SGND:  All GND terminals are the same.  SGND has a self-resetting thermal fuse in series with GND.

10UA/200UA:  Fixed current sources providing 10µA/200µA at a max voltage of about 3 volts.

FIO#/EIO#/CIO#/MIO#:  These are the 23 digital I/O, and are also referred to as DIO0-DIO22.  Besides basic digital I/O operations, some of these terminals can also be configured with Extended Features (frequency input, PWM output, etc.), and all can be configured for various serial protocols: I2C serial, SPI serial, SBUS serial (EI-1050, SHT sensors), 1-Wire serial, and Asynchronous serial.

AIN#:  AIN0-AIN13 are the 14 analog inputs.

DAC#:  DAC0 & DAC1 are the 2 analog outputs.  Each DAC can be set to a voltage between about 0.01 and 5 volts with 12-bits of resolution.

For information about reading inputs, start with the Communication section.  For information about setting outputs, start with the Waveform Generation Application Note.

Figure 4.2-2. Block Diagram

Figure 4.2-3. Wiring Diagram Objects

These wiring diagram objects are intended to be useful for making your own wiring diagrams. Let us know if they are helpful or you would like to see something else. Open this link to make a copy to your own Google Drive.

T8 Hardware Overview

The T8 has 4 different I/O areas:

  • Communication Edge: The T8 has a USB Type-B connector and a RJ45 Ethernet Jack.

  • Miscellaneous Screw Terminal Edge: This screw terminal edge has connections for both analog outputs, 8 digital I/O, and the reference voltage. Screw terminals on this edge are arranged in blocks of 4, with each block consisting of VS, GND, and two I/O. Also on this edge are two LEDs. The Comm LED generally blinks with communication traffic, while the Status LED is used for other indications.

  • Analog Input Screw Terminal Edge: This screw terminal edge has connections for 8 analog inputs.

  • DB Edge: The DB Edge has a 15-pin female D-sub type connector (DB15) which has 12 digital I/O called EIO and CIO.

Figure 4.3-1. Enclosure & Connectors

USB:  Can be used for host communication. Power can be provided through this connector.

Ethernet:  10/100Base-T Ethernet connection can be used for host communication. Power can be provided through this connector.

LEDs:  The Power and Status LEDs convey information about the state of the device, and current operations.

VS:  All VS terminals are the same.  These are outputs that can be used to source about 5 volts.

GND:  All GND terminals are the same.

3.3V:  Fixed reference voltage providing 3.3 V at up to 100 mA.

FIO#/EIO#/CIO#:  These are the 20 digital I/O. They are also referred to as DIO0-DIO19. All DIO can be configured for output low, high (3.3V) and input. Some DIO can also be configured to run Extended Features (frequency input, PWM output, etc.). All can be configured for various serial protocols: I2C serial, SPI serial, SBUS serial (EI-1050, SHT sensors), 1-Wire serial, and Asynchronous serial.

AIN#:  AIN0-AIN7 are the 8 analog inputs.

DAC#:  DAC0 & DAC1 are the 2 analog outputs.  Each DAC can be set to a voltage between about -0.01 and 10.3 volts with 16-bits of resolution. Each DAC can supply up to 20 mA without significant change to the output voltage.

For information about reading inputs, start in Section 3.  For information about setting outputs, start with the Waveform Generation Application Note.

Figure 4.3-2. Block Diagram

Hardware Revisions

T4 Hardware Revisions:

  • 1.2: Initial Release of the T4.

T7 Hardware Revisions:

  • 1.31: Initial release of the T7.

  • 1.35: Several changes were made to improve testing and manufacturing reliability.

  • 1.35a: Switched to a new flash chip. Previous one was discontinued by the manufacturer. This version will not operate properly if a firmware version lower than 1.0218 is installed. Attempting to load firmware below 1.0218 will cause an error to be thrown.

T7-OEM Hardware Revisions:

Same revision history as T7 hardware.  HW 1.35 also changed the style of LEDs that are installed.  HW 1.31 came with through hole LEDs.  HW 1.35 has SMD LEDs installed next to the through hole component locations making them easier to remove.  They also draw less power and are lower profile.

T8 Hardware Revisions:

  • 1.2: Initial release of the T8.

  • 1.3: Added capacitors to improve reading analog signals when the negative input is connected to a high impedance source.

General Device Registers

The following list of registers provide general device information:

System Reboot

It is possible to reset T-series devices remotely using the following SYSTEM_REBOOT register.

System Timing Registers

T-series devices support several registers that are useful for system timing. The core timer runs at 1/2 the LabJack core clock speed. See Appendix A-5 for device clock specifications.

Example

You can use the core timer to measure small time intervals between LabJack commands. For example, say you acquire the following two core timer readings within a brief period of time:

coreTicksRead1 = 12356

coreTicksRead2 = 323212

diffCoreTimerTicks = coreTicksRead2 - coreTicksRead1 = 310856

You can convert the difference between these readings to a difference in time. For example, lets say your T-series device has a core clock that runs at 80 MHz (not applicable to all T-series devices). The core timer would run at 80 MHz / 2 = 40 MHz. We can equivalently call this 40,000,000 clock ticks/second. From here, we can do unit conversion to find the time between the two core timer readings:

diffCoreTimerSeconds = diffCoreTimerTicks / coreTicksPerSecond = 310856 / 40000000 ≈ 0.00777 seconds

The amount of time that passed between the two core timer reads was roughly 0.00777 seconds.

The core timer resolution is defined as 1 / coreTicksPerSecond. In the 40 MHz core timer example above, the resolution is 1 / 40000000 = 25 ns.

RAM

T-Series devices use shared memory. The shared memory allows users to allocate resources to optimize the feature set of the device. The following table describes the available RAM by device:

Device

Heap Size

T4

64 kB

T7

64 kB

T8

384 kB

Many features will allocate memory when they are enabled, and hold that memory until disabled. Others will only use memory while they are active. Here is a list of features which require shared memory:

  • AIN_EF - Some memory is allocated when enabled, more can be allocated during operation.

  • Lua Scripting Engine - Memory usage depends on the size of the script and the memory usage of the script.

  • Stream buffers - Allocated when stream is enabled.

  • StreamOut buffers - Allocated when a StreamOut channel is enabled. 

  • USER_RAM FIFOs - Allocated when enabled.

  • Asynchronous Serial - Allocated when enabled

  • File IO - Allocated to store specified paths.

When there is insufficient memory available, a SYSTEM_MEMORY_BEREFT error will be thrown. Some ideas to free up memory:

  • To free allocated stream RAM, stop stream. To use less stream RAM, use a smaller STREAM_BUFFER_SIZE_BYTES and/or smaller STREAM_OUT#(0:3)_BUFFER_ALLOCATE_NUM_BYTES

  • To free other allocated RAM:

  • Write 0 LUA_RUN

  • Write 0 USER_RAM_FIFO#(0:3)_ALLOCATE_NUM_BYTES

  • Write 0 AIN#(0:149)_EF_INDEX

RAM-Allocating Registers

The below registers allocate system RAM (and may return SYSTEM_MEMORY_BEREFT):

STREAM_BUFFER_SIZE_BYTES does not allocate RAM, but it does set the amount of RAM allocated by STREAM_ENABLE. LJM_eStreamStart writes to STREAM_ENABLE.

Similarly, STREAM_OUT#(0:3)_BUFFER_ALLOCATE_NUM_BYTES does not allocate RAM, but sets the amount of RAM allocated by STREAM_OUT#(0:3)_ENABLE.

Lua scripts dynamically allocate RAM.

Pre-Allocated User RAM Registers

User RAM consists of a list of volatile Modbus addresses where data can be sent to, and read from, a Lua script. Lua writes to the Modbus registers, and then a host device can read that information. 

There are a total of 200 registers of pre-allocated RAM, which is split into several groups so that users may access it conveniently with different data types.

Use the following USER_RAM registers to store information:

Power Mode Registers - T4/T7 Only

The following registers are unsupported on the T8. These registers can be used to reduce the device power consumption. We recommend that most users do not change these registers. See the power consumption charts in Appendix-A-5.

JavaScript errors detected

Please note, these errors can depend on your browser setup.

If this problem persists, please contact our support.