13.2.3 PWM Out with Phase [T-Series Datasheet] | LabJack
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13.2.3 PWM Out with Phase [T-Series Datasheet]



T4 Capable DIO: DIO6, DIO7 (aka FIO6, FIO7)


T7 Capable DIO: DIO0, DIO2, DIO3, DIO4, DIO5 (aka FIO0, FIO2, FIO3, FIO4, FIO5)

Requires Clock Source: Yes

Index: 1

Streamable: No

This PWM Out with Phase Extended Feature is similar to the PWM Out DIO-EF, but allows for phase control.


PWM Output with Phase control generates PWM waveforms with the pulse positioned at different points in the period. This is achieved by setting the DIO line high and low relative to the clock source's count.

Clock#Frequency = CoreFrequency / DIO_EF_CLOCK#_DIVISOR  // typically 80M/Divisor
PWMFrequency = Clock#Frequency / DIO_EF_CLOCK#_ROLL_VALUE

When the count matches CONFIG_B, the DIO line will be set high. When the count matches CONFIG_A, the line will be set low. Therefore CONFIG_B minus CONFIG_A controls the duty cycle.

CoreFrequency is always 80 MHz at this time, but in the future some low-power operational modes might result in different core frequencies.  The valid values for DIO_EF_CLOCK#_DIVISOR are 1, 2, 4, 8, 16, 32, 64, or 256, and a value of 0 (default) equates to a divisor of 1.  For more details about Clock#Frequency and DIO_EF_CLOCK#_DIVISOR, see the DIO-EF Clock Source section.

The clock roll value can take up to one PWM period to update and this does not block subsequent commands from being processed. It is possible to finish updating DIO_EF_CONFIG_A or DIO_CONFIG_B to a value greater than the non-updated clock roll value (which is invalid) but less than the updated clock roll value (which is valid) and throw the error 2565: EF_VALUE_GREATER_THAN_PERIOD.
Potential fixes:
  • disable and re-enable the clock line before updating the clock roll value and duty cycle value.
  • Delay for greater than one "non-updated" PWM period between updating the clock roll value and updating the duty cycle value


DIO#_EF_ENABLE: 0 = Disable, 1 = Enable
DIO#_EF_OPTIONS: Bits 0-2 specify which clock source to use ... 000 for Clock0, 001 for Clock1, and 010 for Clock2. All other bits reserved and should be set to 0.
DIO#_EF_CONFIG_A: When the clock source's count matches this value the line will transition from high to low.
DIO#_EF_CONFIG_B: When the clock source's count matches this value the line will transition from low to high.
DIO#_EF_CONFIG_C: Not used.
DIO#_EF_CONFIG_D: Not used.


The duty cycle can be updated at any time. To update, write the new value to CONFIG_A then CONFIG_B. The value written to CONFIG_A is stored until CONFIG_B is written. After writing CONFIG_B, the new value will be loaded at the start of the next period. Updates are glitch-less unless switching from a very high to very low duty cycle or a very low to very high duty cycle.

DIO#_EF_CONFIG_A: Values written here will set the new falling position. The new value will not take effect until CONFIG_B is written.
DIO#_EF_CONFIG_B: Values written here will set the new rising position. When CONFIG_B is written, the new CONFIG_A is also loaded.


No information is returned by PWM Out with Phase.


Reset has no affect on this feature.


See 13.2.2 PWM Out for an example.