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Software & Driver

 

13.2.2 PWM Out [T-Series Datasheet]

Overview

 

T4 Capable DIO: DIO6, DIO7 (aka FIO6, FIO7)

 

T7 Capable DIO: DIO0, DIO2, DIO3, DIO4, DIO5 (aka FIO0, FIO2, FIO3, FIO4, FIO5)

Requires Clock Source: Yes

Index: 0

Streamable: No

This PWM Out Extended Feature generates a pulse width modulated wave form.

Operation

PWM output will set the DIO high and low relative to the clock source's count. When the count is zero the DIO line will be set high. When the count matches Config A the line will be set low. Therefore Config A is used to control the duty cycle and the resolution is equal to the roll value.

Clock#Frequency = CoreFrequency / DIO_EF_CLOCK#_DIVISOR   // typically 80M/Divisor
PWMFrequency = Clock#Frequency / DIO_EF_CLOCK#_ROLL_VALUE
DutyCycle% = 100 * DIO#_EF_CONFIG_A / DIO_EF_CLOCK#_ROLL_VALUE

For the common case of CoreFrequency = 80 MHz we can rewrite output frequency as:

PWMFrequency = 80M / (DIO_EF_CLOCK#_DIVISOR * DIO_EF_CLOCK#_ROLL_VALUE)

... and for 50% duty-cycle (square wave) simply set:

DIO#_EF_CONFIG_A = DIO_EF_CLOCK#_ROLL_VALUE / 2

CoreFrequency is always 80 MHz at this time, but in the future some low-power operational modes might result in different core frequencies.

The valid values for DIO_EF_CLOCK#_DIVISOR are 1, 2, 4, 8, 16, 32, 64, or 256, and a value of 0 (default) equates to a divisor of 1.  For more details about Clock#Frequency and DIO_EF_CLOCK#_DIVISOR, see the DIO-EF Clock Source section.

PWM Out is capable of glitch-free updates in most situations. A glitch-free update means that the PWM will finish the current period consisting of the high time then the low time before loading the new value. The next period will then have the new duty cycle. This is true for all cases except zero. When setting the duty cycle to zero, the line will be set low regardless of the current position. This means that a single high pulse with duration between zero and the previous high time can be output before the line goes low.

Configure

DIO#_EF_ENABLE: 0 = Disable, 1 = Enable
DIO#_EF_INDEX: 0
DIO#_EF_OPTIONS: Bits 0-2 specify which clock source to use ... 000 for Clock0, 001 for Clock1, and 010 for Clock2. All other bits are reserved and should be set to 0.
DIO#_EF_CONFIG_A: When the specified clocks source's count matches this value, the line will transition from high to low.
DIO#_EF_CONFIG_B: Not used.
DIO#_EF_CONFIG_C: Not used.
DIO#_EF_CONFIG_D: Not used.

Update

The duty cycle can be updated at any time. To update, write the new value to DIO#_EF_CONFIG_A. The new value will not be used until the clock source rolls to zero. This means that at the end of the current period, the new value will be loaded—resulting in a glitch-free transition.

Read

No information is returned by PWM Out.

Reset

Reset has no affect on this feature.

Example

To generate a 10 kHz PWM starting at 25% DC, first configure the clock source.  The higher the roll value, the greater the duty cycle resolution will be. For the highest resolution, we want to maximize the roll value, so use the smallest clock divisor that will not result in a roll value greater than the clock source's maximum (32-bits or 16-bits). With a divisor of 1, the roll value will be 8000:

80 MHz / (1 * 8000) = 10 kHz

Now set the clock registers accordingly:

DIO_EF_CLOCK0_ENABLE = 0
DIO_EF_CLOCK0_DIVISOR = 1
DIO_EF_CLOCK0_ROLL_VALUE = 8000
DIO_EF_CLOCK0_ENABLE = 1

Once the clock source is configured, we can use the roll value to calculate CONFIG_A:

DC = 25% = 100 * CONFIG_A / 8000

...So CONFIG_A = 2000. Now the PWM can be turned on by writing the proper registers:

DIO0_EF_ENABLE = 0
DIO0_EF_INDEX = 0
DIO0_EF_CONFIG_A = 2000
DIO0_EF_ENABLE = 1