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App Notes

Software & Driver

 

13.2.8 High-Speed Counter [T-Series Datasheet]

Overview

Capable DIO: DIO16, DIO17, DIO18, DIO19 (aka CIO0, CIO1, CIO2, CIO3)

Requires Clock Source: No

Index: 7

Streamable: Yes—integer READ registers only.

T-series devices support up to 4 high-speed rising-edge counters that use hardware to achieve high count rates. These counters are shared with other resources as follows:

  • CounterA (DIO16/CIO0): Used by EF Clock0 & Clock1.
  • CounterB (DIO17/CIO1): Used by EF Clock0 & Clock2.
  • CounterC (DIO18/CIO2): Always available.
  • CounterD (DIO19/CIO3): Used by stream mode.

Configure

DIO#_EF_ENABLE: 0 = Disable, 1 = Enable
DIO#_EF_INDEX: 7
DIO#_EF_OPTIONS: Not used.
DIO#_EF_CONFIG_A: Not used.
DIO#_EF_CONFIG_B: Not used.
DIO#_EF_CONFIG_B: Not used.
DIO#_EF_CONFIG_B: Not used.

Update

No update operations can be performed with High-Speed Counter.

Read

Results are read from the following register.

DIO#_EF_READ_A: Returns the current count which is incremented on each rising edge.

Stream Read

All operations discussed in this section are supported in command-response mode.  In stream mode, you can read from the integer READ registers (A, B, A_AND_RESET), but as mentioned in the Stream Section those reads only return the lower 16 bits so you need to also use STREAM_DATA_CAPTURE_16 in the scan list to get the upper 16 bits.

Reset

DIO#_EF_READ_A_AND_RESET: Reads the current count then clears the counter. There is a brief period of time between reading and clearing during which edges can be missed. During normal operation this time period is 10-30 µs. If missed edges at this point are not acceptable, then do not use reset but rather just note the "virtual reset" counter value in software and subtract it from other values.

Frequency Measurement

Counters are often used to measure frequency by taking change in count over change in time:

Frequency = (CurrentCount - PreviousCount) / (CurrentTimestamp - PreviousTimestamp)

Typically the timestamps are from the host clock (software), but for more accurate timestamps read the CORE_TIMER register (address=61520, UINT32) in the same Modbus packet as the READ registers.  CORE_TIMER is a 32-bit system timer running at 1/2 the core speed, and thus is normally 80M/2 => 40 MHz.

Also note that other digital extended features are available to measure frequency by timing individual pulses rather than counting over time.

Example

Enable CounterC on DIO18/CIO2:

DIO18_EF_ENABLE = 0
DIO18_EF_INDEX = 7
DIO18_EF_ENABLE = 1

Results can be read from the READ registers defined above.

Edge Rate Limits

See Appendix A-2.