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A-4 Analog Output [T-Series Datasheet]

Specifications for analog output channels (DAC0 and DAC1) are shown below.

Table A4-1. T4 DAC Information

  Conditions Min Typical Max Units
Nominal Output Range [1] No Load TBD   TBD Volts
  @ ±2.5 mA TBD   TBD Volts
Resolution     10   Bits
Absolute Accuracy 5% to 95% FS   ±TBD   % FS
Integral Linearity Error     ±TBD ±TBD counts
Differential Linearity Error     ±TBD ±TBD counts
Noise [2]     ±TBD   μV
Source Impedance [3]     50   Ω
Current Limit [4] Max to GND   TBD   mA
Time Constant     TBD   μs
           
[1] Maximum and minimum analog output voltage is limited by the supply voltages (VS and GND). The specifications assume VS is 5.0 volts. Also, the ability of the DAC output buffer to driver voltages close to the power rails, decreases with increasing output current.     
[2] TBD    
[3] For currents up to about TBDmA, this source impedance dominates the error due to loading. For example, if you load DAC0 with a 1000 ohm resistor from DAC0 to GND, and set DAC0 to 3.0V, the actual voltage at the DAC0 terminal will be about 3.0*1000/(50+1000) = 2.86V. For currents > TBDmA, you increasingly get added droop due to the ability of the output buffer to drive substantial current close to the power rails.     
[4] The output buffer will limit current to about TBDmA and can maintain this value continuously without damage. Take, for example, a 100 ohm resistor from DAC0 to GND, with the internal source impedance of 50 ohms, and DAC0 set to 4.5V. A simple calculation would predict a current of 4.5/(50+150) = 30mA, but the output buffer will limit the current to TBDmA. A simple calculation taking into account only the voltage droop due to the internal 50 ohm resistance would predict a voltage at the DAC0 terminal of 4.5*100/(50+100) = 3.0V, but since the current is limited to TBDmA the actual voltage at DAC0 would be more like 100*0.02 = 2.0V.     

 

Table A4-2. T7 DAC Information

  Conditions Min Typical Max Units
Nominal Output Range [1] No Load 0.01   4.99 Volts
  @ ±2.5 mA 0.25   4.75 Volts
Resolution     12   Bits
Absolute Accuracy 5% to 95% FS   ±0.06   % FS
Integral Linearity Error     ±1.5 ±2 counts
Differential Linearity Error     ±0.25 ±0.5 counts
Noise [2]     ±100   μV
Source Impedance [3]     50   Ω
Current Limit [4] Max to GND   20   mA
Time Constant     4   μs
           
[1] Maximum and minimum analog output voltage is limited by the supply voltages (VS and GND). The specifications assume VS is 5.0 volts. Also, the ability of the DAC output buffer to driver voltages close to the power rails, decreases with increasing output current.     
[2] With load, the noise increases if operating too close to VS. With a 1000 ohm load, noise increases noticeably at 4.4V and higher. With a 330 ohm load, noise increases noticeably at 3.7V and higher. With a 100 ohm load, noise increases noticeably at 2.7V and higher.     
[3] For currents up to about 8mA, this source impedance dominates the error due to loading. For example, if you load DAC0 with a 1000 ohm resistor from DAC0 to GND, and set DAC0 to 3.0V, the actual voltage at the DAC0 terminal will be about 3.0*1000/(50+1000) = 2.86V. For currents > 8mA, you increasingly get added droop due to the ability of the output buffer to drive substantial current close to the power rails.     
[4] The output buffer will limit current to about 20mA and can maintain this value continuously without damage. Take, for example, a 100 ohm resistor from DAC0 to GND, with the internal source impedance of 50 ohms, and DAC0 set to 4.5V. A simple calculation would predict a current of 4.5/(50+150) = 30mA, but the output buffer will limit the current to 20mA. A simple calculation taking into account only the voltage droop due to the internal 50 ohm resistance would predict a voltage at the DAC0 terminal of 4.5*100/(50+100) = 3.0V, but since the current is limited to 20mA the actual voltage at DAC0 would be more like 100*0.02 = 2.0V.