Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the total time is spent low (out of 65536 total increments). That means the duty cycle can be varied from 100% (0 out of 65536 are low) to 0.0015% (65535 out of 65536 are low).

The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2¹⁶. The following table shows the range of available PWM frequencies based on timer clock settings.

Table 2.10.1.1-1. 16-bit PWN Frequency Ranges

The same clock applies to all timers, so all 16-bit PWM channels will have the same frequency and will have their falling edges at the same time.

PWM output starts by setting the digital line to output-low for the specified amount of time. The output does not necessarily start instantly, but rather has to wait for the internal clock to roll. For 16-bit PWM output, the start delay varies from 0.0 to TimerClockDivisor*65536/TimerClockBase. For example, if TimerClockBase = 48 MHz and TimerClockDivisor = 1, PWM frequency is 732 Hz, PWM period is 1.4 ms, and the start delay will vary from 0 to 1.4 ms.

If a duty cycle of 0.0% (totally off) is required, consider using a simple inverter IC such as the CD74ACT540E from TI.

Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the total time is spent low (out of 65536 total increments). The lower byte is actually ignored since this is 8-bit PWM. That means the duty cycle can be varied from 100% (0 out of 65536 are low) to 0.4% (65280 out of 65536 are low).

The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2⁸. The following table shows the range of available PWM frequencies based on timer clock settings.

Table 2.10.1.2-1. 8-bit PWN Frequency Ranges

The same clock applies to all timers, so all 8-bit PWM channels will have the same frequency and will have their falling edges at the same time.

PWM output starts by setting the digital line to output-low for the specified amount of time. The output does not necessarily start instantly, but rather has to wait for the internal clock to roll. For 8-bit PWM output, the start delay varies from 0.0 to TimerClockDivisor*256/TimerClockBase. For example, if TimerClockBase = 48 MHz and TimerClockDivisor = 256, PWM frequency is 732 Hz, PWM period is 1.4 ms, and the start delay will vary from 0 to 1.4 ms.

If a duty cycle of 0.0% (totally off) is required, consider using a simple inverter IC such as the CD74ACT540E from TI.

Mode 2: On every rising edge seen by the external pin, this mode records the number of clock cycles (clock frequency determined by TimerClockBase/TimerClockDivisor) between this rising edge and the previous rising edge. The value is updated on every rising edge, so a read returns the time between the most recent pair of rising edges.

In this 32-bit mode, the Control processor must jump to an interrupt service routine to record the time, so small errors can occur if another interrupt is already in progress. The possible error sources are:

• Other edge interrupt timer modes (2/3/4/5/8/9/12/13). If an interrupt is already being handled due to an edge on another timer, delays of a couple microseconds per timer are possible. That means if five other edge detecting timers are enabled, it is possible (but not likely) to have about 10 microseconds of delay.
• If a stream is in progress, every sample is acquired in a high-priority interrupt. These interrupts could cause delays of up to 10 microseconds.
• The always active UE9 system timer causes an interrupt 11.4 times per second. If this interrupt happens to be in progress when the edge occurs, a delay of about 1 microsecond is possible. If the software watchdog is enabled, the system timer interrupt takes longer to execute and a delay of a few microseconds is possible.

Note that the minimum measurable period is limited by the edge rate limit discussed in Section 2.10.2.

Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.

Mode 3 is the same except that falling edges are used instead of rising edges.

Records the high and low time of a signal on the external pin, which provides the duty cycle, pulse width, and period of the signal.  Returns 4 bytes, where the first two bytes (least significant word or LSW) are a 16-bit value representing the number of clock ticks during the high signal, and the second two bytes (most significant word or MSW) are a 16-bit value representing the number of clock ticks during the low signal.  The clock frequency is determined by TimerClockBase/TimerClockDivisor. 

The appropriate value is updated on every edge, so a read returns the most recent high/low times.  Note that a duty cycle of 0% or 100% does not have any edges.

To select a clock frequency, consider the longest expected high or low time, and set the clock frequency such that the 16-bit registers will not overflow.  In other words, to measure 0% to 100% duty cycle for a given signal frequency, you need to set your clock frequency low enough such that the overall period of the signal is less than 65535 * 1/TimerClockFrequency.  That equates to:

fclock  ≤  65535 * fsignal

Note that the minimum measurable high/low time is limited by the edge rate limit discussed in Section 2.10.2.

When using the LabJackUD driver the value returned is the entire 32-bit value.  To determine the high and low time this value should be split into a high and low word.  One way to do this is to do a modulus divide by 2^16 to determine the LSW, and a normal divide by 2^16 (keep the quotient and discard the remainder) to determine the MSW.

Writing a value of zero to the timer performs a reset.  After reset, a read of the timer value will return zero until a new edge is detected.  If a timer is reset and read in the same function call, the read returns the value just before the reset.  The duty cycle reset is special, in that if the signal is low at the time of reset, the high-time/low-time registers are set to 0/65535, but if the signal is high at the time of reset, the high-time/low-time registers are set to 65535/0.  Thus if no edges occur before the next read, it is possible to tell if the duty cycle is 0% or 100%.

On every rising edge seen by the external pin, this mode increments a 32-bit register. Unlike the pure hardware counters, these timer counters require that the firmware jump to an interrupt service routine on each edge.

Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.

Intended for frequencies less than 10 Hz, this mode adds a debounce feature to the firmware counter, which is particularly useful for signals from mechanical switches. On every applicable edge seen by the external pin, this mode increments a 32-bit register. Unlike the pure hardware counters, these timer counters require that the firmware jump to an interrupt service routine on each edge.

When configuring only (UpdateConfig=1), the low byte of the timer value is a number from 0-255 that specifies a debounce period in 87 ms increments (plus an extra 0-87 ms of variability):

Debounce Period = (0-87 ms) + (TimerValue * 87 ms)

In the high byte (bits 8-16) of the timer value, bit 0 determines whether negative edges (bit 0 clear) or positive edges (bit 0 set) are counted.

Assume this mode is enabled with a value of 1, meaning that the debounce period is 87 ms and negative edges will be counted. When the input detects a negative edge, it increments the count by 1, and then waits 87 ms before re-arming the edge detector. Any negative edges within the 87 ms debounce period are ignored. This is good behavior for a normally-high signal where a switch closure causes a brief low signal. The debounce period can be set long enough so that bouncing on both the switch closure and switch open is ignored.

When only updating and not configuring, writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.

Outputs a square wave at a frequency determined by TimerClockBase/TimerClockDivisor divided by 2*Timer#Value. The Value passed should be between 0-255, where 0 is a divisor of 256. By changing the clock configuration and timer value a wide range of frequencies can be output. The maximum frequency is 48000000/2 = 24 MHz. The minimum frequency is (750000/256)/(2*256) = 5.7 Hz.

The frequency output has a -3 dB frequency of about 10 MHz on the FIO lines. Accordingly, at high frequencies the output waveform will get less square and the amplitude will decrease.

The output does not necessarily start instantly, but rather has to wait for the internal clock to roll. For the Frequency Output mode, the start delay varies from 0.0 to TimerClockDivisor*256/TimerClockBase. For example, if TimerClockBase = 48 MHz and TimerClockDivisor = 256, the start delay will vary from 0 to 1.4 ms.

Requires 2 timer channels used in adjacent pairs (0/1, 2/3, or 4/5). Even timers will be quadrature channel A, and odd timers will be quadrature channel B. The UE9 does 4x quadrature counting, and returns the current count as a signed 32-bit integer (2’s complement). The same current count is returned on both even and odd timer value parameters.

Writing a value of zero to either or both timers performs a reset of both. After reset, a read of either timer value will return zero until a new quadrature count is detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.

4X Counting

Quadrature mode uses the very common 4X counting method, which provides the highest resolution possible.  That means you get a count for every edge (rising & falling) on both phases (A & B).  Thus if you have an encoder that provides 32 PPR, and you rotate that encoder forward 1 turn, the timer Value register will be incremented by +128 counts.

Z-phase support

Quadrature mode supports Z-Phase. When enabled this feature will set the count to zero when the specified IO line sees a logic high.

Z-phase is controlled by the value written to the timer during initialization. To enable z-phase support set bit 15 to 1 and set bits 0 through 4 to the DIO number that Z is connected to. EG: for a Z-line on EIO3 set the timer value to 0x800B or 32779. This value should be sent to both the A and B timers.

Note that the LabJack will only check Z when it sees an edge on A or B.

Z-phase support requires Control Firmware 2.11 or later.

2's Complement

Other timer modes return unsigned values, but this timer mode is unique in that it returns a signed value from -2147483648 to +2147483647.  That is, a 32-bit 2's complement value.  When you do a timer value read and get back a single float from the UD driver, the math is already done and you get back a value from -2147483648.0 to +2147483647.0, but when using the special channels 20x/23x/224 you get the LSW and MSW separately and have to do the math yourself.  Search for 2's complement math for your particular programming language.

In a language such as C++, you start by doing using unsigned 32-bit variables & constants to compute Value = (MSW * 65536) + LSW.  Then simply cast Value to a signed 32-bit integer.

In a language such as Java that does not support unsigned integers, do everything with signed 64-bit variables & constants.  First calculate Value = (MSW * 65536) + LSW.  If Value < 2147483648, you are done.  If Value >= 2147483648, do ActualValue = -1 * (4294967296 - Value).

This mode should only be assigned to odd numbered timers (1, 3, or 5).  On every rising edge seen by the external pin, this mode increments a 16-bit register.  When that register matches the specified timer value (stop count value), the adjacent even timer is stopped (0/1, 2/3, or 4/5).  The range for the stop count value is 1-65535.  Generally, the signal applied to this timer is from the adjacent even timer, which is configured in some output timer mode.  One place where this might be useful is for stepper motors, allowing control over a certain number of steps.

Note that the timer is counting from the external pin like other input timer modes, so you must connect something to the stop timer input pin.  For example, if you are using Timer1 to stop Timer0 which is outputting pulses, you must connect a jumper from Timer0 to Timer1.

Once this timer reaches the specified stop count value, and stops the adjacent timer, the timers must be reconfigured (set the UpdateConfig bit for both timers, setting the UpdateConfig for just the output timer will restart the output in continuous mode) to restart the adjacent timer, or the timer can be restarted by rewriting the value to the stop timer.

When the adjacent even timer is stopped, it is still enabled but just not outputting anything.  Thus rather than returning to whatever previous digital I/O state was on that terminal, it goes to the state “digital-input” (which has a 100 kΩ pull-up to 3.3 volts). That means the best results are generally obtained if the terminal used by the adjacent even timer was initially configured as digital input (factory default), rather than output-high or output-low.  This will result in negative going pulses, so if you need positive going pulses consider using a simple inverter IC such as the CD74ACT540E from TI.

The MSW of the read from this timer mode returns the number of edges counted, but does not increment past the stop count value.  The LSW of the read returns edges waiting for.

The LabJack UE9 has a free-running internal 64-bit system timer with a frequency of 750 kHz. Timer modes 10 & 11 return the lower or upper 32-bits of this timer. An FIO line is allocated for these modes like normal, even though they are internal readings and do not require any external connections.

Similar to the 32-bit edge-to-edge timing modes described above (modes 2 & 3), except that hardware capture registers are used to record the edge times. This limits the times to 16-bit values, but is accurate to the resolution of the clock, and not subject to any errors due to firmware processing delays.

Note that the minimum measurable period is limited by the edge rate limit discussed in Section 2.10.2.