Activity on I/O during Labjack Booting | LabJack
 

Activity on I/O during Labjack Booting

2 posts / 0 new
Last post
Chetan Lad
Chetan Lad's picture
Activity on I/O during Labjack Booting

i worked on all Labjack unit (U3, U6 & T7) and i observed that, when LABJACK unit is booting up that time ALL Digital I/O have some Capacitor charging type response in microsec. This response is problematic for me. so i want to know how i can avoid this response? I request to LABJACK designer, please make some circuit on Digital I/O for when labjack unit is booting up that time all I/O's are at state low/high condition.   

LabJack Support
LabJack Support's picture
Following is some applicable

Following is some applicable information from the U6 Datasheet:

https://labjack.com/support/datasheets/u6/hardware-description/dio

All digital I/O on the U6 have 3 possible states: input, output-high, or output-low. Each bit of I/O can be configured individually. When configured as an input, a bit has a ~100 kΩ pull-up resistor to 3.3 volts (all digital I/O are 5 volt tolerant). When configured as output-high, a bit is connected to the internal 3.3 volt supply (through a series resistor). When configured as output-low, a bit is connected to GND (through a series resistor).

The power-up condition of the digital I/O can be configured by the user with the "Config Defaults" option in LJControlPanel.  From the factory, all digital I/O are configured to power-up as inputs. Note that even if the power-up default for a line is changed to output-high or output-low, there is a delay of about 100 ms at power-up where all digital I/O are in the factory default condition.

1.  Digital I/O have 3 states (i.e. they are "tristate" I/O).  Input (100 kohms to 3.3V), Output-high (180/550 ohms to 3.3V), and Output-low (180/550 ohms to 0V).

2.  During boot-up there is a point in time where the microcontroller hardware is powered up, but firmware has not executed enough yet to configure anything.  During this time the digital I/O hardware is in its default state of Input.

In some systems this behavior can cause a problem.  For example, say the user has a device with a high impedance (low current) input that is watching for a logic high signal to indicate an alarm condition.  The user connects FIO0 from the U6 to this alarm input and the user also configures the power-up default of FIO0 to be output-low.  Whenever the U6 boots-up there will be some time (~100ms) where FIO0 is configured as input, meaning that it is weakly (~100k) pulled to 3.3V.  Since the alarm input in this example is high impedance, this 3.3V source could be enough to signal a high to the alarm input even though the 3.3V has 100k of source impedance.  If the alarm input draws less than 13 uA the voltage will stay at 2.0V or higher and might look like a logic high.

Some typical solutions:

1.  Add a 10k resistor from FIO0 to GND.  When FIO0 is set to input the 10k forms a voltage divider with the internal 100k and the resulting voltage on FIO0 is only about 0.3V.  When FIO0 is set to output-high, there is a still divider but only with the internal 550 ohms so the resulting voltage on FIO0 is about 3.1V.

2.  Along the same lines as #1, you can increase the current draw of the load.  Add a 10k resistor from the Alarm input to ground and it will have the same effect as in #1.

3.  Use the sinking configuration to control the load.  In this configuration you set FIO0 to Input to turn the load off, and set FIO0 to output-low to turn the load on.  See the Controlling Relays App Note.

4.  Use the LJTick-RelayDriver in between FIO0 and the load.  The LJTRD switch is on when FIO0 is set to output-high, and off when FIO0 is set to output-low or input.

5.  Add some sort of filter (e.g. RC) to the line such that it has to be in a given state for a long time before the output voltage rises/falls.