### Source Impedance and Analog Measurements

A commonly overlooked detail when measuring analog voltages with data acquisition hardware is the voltage source's output impedance.  Subtle interactions between the voltage source and the T7's analog to digital converter (ADC) circuitry can result in erroneous readings in certain situations.  This application note describes issues caused by voltage source impedance, and how to approach measurements to ensure the greatest accuracy.  This application references the T7 hardware specifically, however the concepts defined within are also valid for other hardware such as the T4, U6, and UE9 devices.

### Static Errors

The ADC hardware is comprised of multiple components used for signal conditioning and analog to digital conversion.  Each component possesses some amount of leakage or bias currents which interact amongst the various components.  The combined effect is a small bias current seen at the analog inputs.  Bias currents are currents that naturally flow into or out of the inputs on the T7.  Since bias currents are inherent to the ADC layer's operation, they cannot be eliminated.

The magnitude of the bias currents are typically very small (nanoamps).  The magnitude will vary to some degree, depending on the voltage applied to the analog inputs.  The details behind bias current reaction with external voltages is complex.  However, the overall affects are easily characterized using one of the two test setups shown in figure 1 and figure 2.

Figure 1 depicts a single-ended test which measures a known variable voltage source on AIN0 and AIN1.  The difference between the voltage at the two inputs is due to the voltage drop across the resistor at AIN0, which is in turn used to calculate the bias current.

Figure 2 depicts a differential test which used for determining bias currents for the positive and negative inputs on a differential input.  The differential measurement on the AIN0-1 pair is subtracted from the differential reading on AIN2-3.  The difference between the two readings is due to the bias current flowing through the input resistor on AIN0.  Note that only one resistor is used at any time, and the calculated bias current only apply to the input the resistor is on.  Figure 1 - Test Setup Figure 2 - Test Setup

Figure 3 depicts typical bias currents for then T7s positive and negative inputs.  The depicted bias current was collected using the differential test setup shown in figure 2.  The single ended case will perform identically to the positive input case since the positive input and single-ended input circuits are identical.  Bias current data was collected at 25C to apply to most applications.  Bias currents are dependent on operating temperature.  It is left to the user to determine bias current effects at operating temperatures other than what is shown.

 Figure 3 - Typical T7 input bias currents.  Positive current is defined as flowing into the T7's inputs.

#### Static Offsets

In practice, bias current show up as voltage offsets across the voltage signal's source resistance.  The error between measured and actual can be either positive or negative depending on the bias current direction.  Figures 4 and 5 depict how bias currents interact with source resistances in single-ended and differential measurements.  Note that the positive direction for current flow is defined as flowing into the T7's inputs.  Figure 4 - SE Schematic Figure 5 - Diff Schematic

Weather or not the bias currents need to be dealt with will ultimately depend on source resistance and accuracy requirements. Single-ended measurement are the easiest to deal with because the static error is simply the expected bias current multiplied by the source resistance.  Differential measurements can be more involved, and the end-effects will depend greatly on the source topology.  Characterization of differential configurations is beyond the scope of this application note, and it is left to the user to test their hardware to determine bias current effects.

### Dynamic Errors

Dynamic errors are erroneous voltage readings caused by the input channel's dynamic response when the hardware switches between input channels.  There are two main components which dictate the input channels dynamic response:

1. Source Impedance
2. Input Impedance Figure 6 - Dynamic circuit components

An input's dynamic response comes into play when the multiplexer switches between channels.  For example, assume a situation where an analog reading just completed on AIN0 when the multiplexer switches to AIN1 to make a new conversion.  The input circuitry is still at the voltage from the previous analog reading after the multiplexer switches (voltage on AIN0).  The residual voltage on the input circuitry must charge/discharge to equilibrium with the current input voltage.  The charging/discharging characteristics depends on the combined source and channel impedance.  The input signal will generally follow some decay or damped oscillation due to the input's combined impedance.  The exact charge/discharge shape is not a concern.  The important concept is the time required for the input signal to come to equilibrium after the multiplexer switches.  The amount of time required for the input to come to equilibrium is dominated by the source resistance and voltage differential between successive analog reading on different channel.  Figure 7 depicts typical decay profiles on an analog input with connected to ground through different resistances.

 Figure 7 - Decay plots

The data in figure 7 was collected from an analog input signal immediately after sampling from a different channel connected to a 10V DC signal.  Figure 8 depicts a simple test setup to measure input channel dynamic response, using an oscilloscope to collect waveform data. Figure 8 - Test Setup

#### Settling Time

Erroneous voltage readings occur when a ADC conversion occurs before a channel's dynamic characteristics have had a chance to decay to accuracy levels.  A short delay is introduced in firmware after the multiplexer switches to prevent such errors from being introduced into analog readings.  This short delay is called settling time and is directly accessible through  AINn_SETTLING_US parameter.  The settling time may be individually set for each input channel where valid values range are 0-50,000.  A settling time value of 0 is reserved for the default settling times (Table 1) and 1-50,000 user defined settling times defined in microseconds.  Table 1 lists the auto settling times (AINn_SETTLING_US = 0) which are suggested for source resistances up to 1k Ohms.

 Table 1 - Auto settling times for various range and resolution index settings.  Auto settling times are adequate for source resistance up to 1k Ohms.

Table 2 lists suggested settling times for source resistances between 1k Ohms and 1M Ohms.  The values listed in the table are suggested values to use as a starting point.  Note that auto settling times are adequate for source resistances in excess of 1k Ohms.

 Table 2 - Suggested settling times for various source resistances [us]. [1.]  Settling times are listed in microseconds. [2.]  OS indicates analog readings did not meet absolute accuracy specifications, using settling times of one second. Additional settling time may be required to achieve desired accuracy.

In certain applications, settling times greater than 50 milliseconds may be required to achieve desired accuracy.  To accommodate these situations the settling time must be implemented in software.  Software implemented settling times are created by taking two consecutive readings on the same channel, separated by some specified delay in software.  The first reading is used two switch the multiplexer to the desired channel only, and is simply ignored.  Next, the software delay for a specified amount of time, allowing the input's dynamic characteristics diminish, achieving full accuracy.  A second analog reading is taken immediately after the delay, resulting in a valid reading.

### Channel Crosstalk

Channel crosstalk is a condition where a time-varying signal on one channel is imposed onto an adjacent channel due to pure electric coupling.   Channel crosstalk is often times confused with the dynamic errors described above.  Extensive design efforts are taken to eliminate channel crosstalk to where it is not an issue.  Please refer to appendix A-3 in the T7 datasheet to review the channel crosstalk specification.

### T7 Sampling Details

When the stream scan goes to acquire a channel, it sets the muxes to connect the channel to the internal in-amp (this actually happens near the start of the last ADC conversion period of the previous channel), then waits the specified settling time, then acquires 1 or more samples from the ADC.  For each sample the ADC sampling cap is connected for only 1 us (ADC acquisition time), then ADC conversion time is about 3.2 us.  The "1 or more samples" part has to do with ResolutionIndex which does oversampling & averaging where ResolutionIndex=1 corresponds to 1 sample, ResolutionIndex=2 corresponds to 2 samples, ResolutionIndex=4 corresponds to 4 samples, and so on up to ResolutionIndex=8 which corresponds to 128 samples. ### T7 sampling parameters

"When the stream scan goes to acquire a channel, it sets the muxes to connect the channel to the internal in-amp (this actually happens near the start of the last ADC conversion period of the previous channel), then waits the specified settling time, then acquires 1 or more samples from the ADC.  For each sample the ADC sampling cap is connected for only 1 us (ADC acquisition time), then ADC conversion time is about 3.2 us.  The "1 or more samples" part has to do with ResolutionIndex which does oversampling & averaging where ResolutionIndex=1 corresponds to 1 sample, ResolutionIndex=2 corresponds to 2 samples, ResolutionIndex=4 corresponds to 4 samples, and so on up to ResolutionIndex=8 which corresponds to 128 samples."

1) For ResolutionIndex>1, what is the interval between subsamples?  It looks like the minimum possible is 4.2 us, but I'd guess you build in a little breathing room and use 5 or 6 us instead.

I ask because I want to balance the error caused by the distributed-in-time sampling with that caused by the noise.  For example, if I use RI=2, the returned average voltage will correspond to a time that is halfway between the times that the two ADC sampling intervals end.  I'd like to know what that time is.

If my signal is linear in time, then adjusting the effective sampling time as I just described will eliminate the distributed-sampling-time error.  If it's not linear in time, then the "time smearing" error will increase as the second derivative of my signal increases.  Knowing the typical characteristics of my signal I can choose RI to best balance noise and time smearing error. (Put another way, the multiple sampling is applying a low-pass filter to my signal, and the filter characteristics depend on the subsampling interval.)

2) if the T7 is acquiring only one channel, is the settling time delay eliminated, or is it still there?  Or is it there only for the first acquisition of the stream and not for later ones? ### 1) For an approximate value

1) For an approximate value we can us (3+settling time)*2^(resolution index -1). However, different firmware versions have small variations. To account for variations the actual stream timing can be measured using the signaling on SPC: https://labjack.com/support/datasheets/t-series/spc

2) When there is only one channel per scan the automatic settling time will be limited to 10 us. Manual settling times can be specified as desired.