5.2.17 - SPI [U6 Datasheet]

Sends and receives serial data using SPI synchronous communication.

Table 5.2.17-1. SPI Command Response

• NumSPIWords: This is the number of SPI bytes divided by 2. If the number of SPI bytes is odd, round up and add an extra zero to the packet.
• SPIOptions: If AutoCS is true, the CS line is automatically driven low during the SPI communication and brought back high when done. If DisableDirConfig is true, this function does not set the direction of the lines, whereas if it is false the lines are configured as CS=output, CLK=output, MISO=input, and MOSI=output. SPIMode specifies the standard SPI mode as discussed below.
• SPIClockFactor: Sets the frequency of the SPI clock according the following approximate formula: Frequency = 1000000/(10+10*(256-SPIClockFactor), where passing a value of 0 corresponds to a factor of 256, and thus a maximum frequency of about 100 kHz.
• Advanced Options: Bit [2:0] allow the number of bits to be transfered during the final byte to be specified, where 0 = 8. This makes it possible to transfer any number of bits within packet size limitations. For example, to transfer 11 bits set the number of bytes to 2 and set bits [2:0] of the advanced options to 3. The LabJack will transfer a full byte of 8 bits, then transfer 3 more bits. The 3 most significant bits in the final byte will be sent and data read during those bits will be in the most significant bits of the final byte in the data. This feature requires firmware 1.21.
• CS/CLK/MISO/MOSI -PinNum: Assigns which digital I/O line is used for each SPI line. Value passed is 0-19 corresponding to the normal digital I/O numbers as specified in Section 2.8.
• NumSPIBytesToTransfer: Specifies how many SPI bytes will be transferred (1-50).

The initial state of SCK is set properly (CPOL), by this function, before CS (chip select) is brought low (final state is also set properly before CS is brought high again). If CS is being handled manually, outside of this function, care must be taken to make sure SCK is initially set to CPOL before asserting CS.

All standard SPI modes supported (A, B, C, and D).

Mode A: CPOL=0, CPHA=0

Mode B: CPOL=0, CPHA=1

Mode C: CPOL=1, CPHA=0

Mode D: CPOL=1, CPHA=1

If Clock Phase (CPHA) is 1, data is valid on the edge going to CPOL. If CPHA is 0, data is valid on the edge going away from CPOL. Clock Polarity (CPOL) determines the idle state of SCK.

Up to 50 bytes can be written/read. Communication is full duplex so 1 byte is read at the same time each byte is written.